Memory Ordering in Modern Microprocessors
A memory barrier, in the sense we’ll concern ourselves here, is an instruction which forces both the CPU to ensure that any preceding reads and/or writes (depending on the type of barrier) are completed before continuing. On most SMP architectures, locking primitives must use them in order to guarantee that client code will have a consistent view of memory after entering or leaving a critical section.
Since the compiler can also reorder reads and writes on its own, it’s often necessary to use memory barrier instructions via inline functions with annotations to force appropriate behavior on the part of the compiler.
Paul McKenny’s 2005 article in Linux Journal, Memory Ordering in Modern Microprocessors, Part I is a good introduction to the properties of contemporary hardware which make the use of memory barriers necessary.
Update: Part II, which describes the behavior of specific architectures, may be of particular interest to the writers of JIT compilers.